N74: Superconducting and Semiconductor Qubits I/O, Packaging, and 3D Integration I

Wed. March 8, 1:30 p.m. – 1:42 p.m. PST

Room 403/404

Accurate on-chip temperature sensing is critical for the characterization and optimization of modern CMOS integrated circuits, as nanometer-scale thin-body technologies such as SOI and FinFETs are susceptible to localized heating due to on-chip power dissipation. The reduced thermal conductivity of silicon at low temperatures exacerbates this localized heating for circuits operating at deep-cryogenic temperatures used in applications such as quantum computing. Deep-cryogenic on-chip thermometry is therefore an essential part of thermal management in quantum computing ICs.

Here, we present a measurement-based comparison of sensitivity and other metrics for a variety of on-chip temperature-sensing methods in a standard SOI process. These include using the well-known temperature dependences of diode and transistor IV characteristics and silicided polysilicon resistivity (used in MOS gate resistance thermometry) as well as using specialized techniques which can only be realised at cryogenic temperatures, such as Fermi-function fitting of Coulomb blockade, and measuring the critical current of thin-film superconductors. When two or more of these techniques are combined, accurate on-chip temperature sensing can be achieved from the milliKelvin range to room temperature.